Not Applicable.
Not Applicable.
The present specification relates generally to fabrication processes for integrated circuits (ICs). More specifically, the present specification relates to a method of fabricating dual gate structures.
The semiconductor industry needs to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This need for large scale integration has led to a continued shrinking of the circuit dimensions and features of the devices.
The ability to reduce the size of structures such as shorter gate lengths in field-effect transistors is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. In current commercial fabrication processes, optical devices expose the photoresist using light having a wavelength of 248 nm (nanometers). Research and development laboratories are experimenting with the 193 nm wavelength to reduce the size of structures. Further, advanced lithographic technologies are being developed that utilize radiation having a wavelength of 157 nm and even shorter wavelengths, such as those used in Extreme Ultra-Violet (EUV) lithography (e.g., 13 nm).
Field effect transistors, such as MOSFETs (metal oxide semiconductor field effect transistors) are widely used in integrated circuits. One application for MOSFETS is in Complementary MOS (CMOS) circuits. CMOS circuits have the advantages of low standby power, high speed, and high noise immunity.
CMOS circuits require a balanced pair of N-and P-channel enhancement-mode devices (e.g., MOSFETS) on the same chip. This is typically achieved by fabricating one device on a substrate having one polarity type (e.g., N) and another in a well doped with an opposite impurity type (e.g., P). However, conventional techniques are unable to further reduce the gate lengths and other features sizes of the CMOS circuit. Further reduction in the gate lengths and other feature sizes is required for improved speed, density, and functionality. While wet trimming has been used to reduce feature sizes, wet trimming has less of a process window.
Accordingly, what is needed is an improved dual gate process. Further, what is needed is a dual gate process that fabricates gates having a smaller gate width than using conventional techniques. Further still, what is needed is a dual gate process that uses gate conductor materials having the same or different work functions. Further yet, what is needed is a dual gate process having a shorter gate length which is controllable by a fabrication parameter, such as, time. The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
According to an exemplary embodiment, a method of forming dual gate structures on first and second portions of a substrate includes: providing an insulative layer over the substrate; providing a first layer of material having a first work function parameter over the first portion of the substrate; providing a second layer of material having a second work function parameter different than the first work function parameter over the second portion of the substrate; providing a third layer of material over the first and second layers of material; providing a self-assembled molecular layer over at least a portion of the third layer of material, wherein the self-assembled molecular layer has regions of etch selectivity; and etching the self-assembled molecular layer at the regions of etch selectivity until gate structures are formed over the first and second portions of the substrate.
According to another exemplary embodiment, an integrated circuit having dual gate structures on first and second portions of a semiconductor substrate is fabricated by the steps of: providing an insulative layer over the substrate; providing a first layer of gate conductor material having a first work function parameter over the first portion of the substrate; providing a second layer of gate conductor material having a second work function parameter different than the first work function parameter over the second portion of the substrate; providing a third layer of gate conductor material over the first and second layers of material, whereby features of the third layer of gate conductor material are provided in both the first and second portions of the substrate; providing a self-assembled molecular layer over at least a portion of the features, wherein the self-assembled molecular layer has regions of etch selectivity; and etching the self-assembled molecular layer at the regions of etch selectivity until gate structures are formed in the first and second portions of the substrate.
According to yet another exemplary embodiment, a method of fabricating dual gate structures for N- and P-channel devices on a semiconductor substrate includes: doping a first portion of the substrate with a dopant suitable for an N-channel device; doping a second portion of the substrate with a dopant suitable for a P-channel device; providing a first layer of gate conductor material over the first portion of the substrate; providing a second layer of gate conductor material over the second portion of the substrate; providing a self-assembled molecular layer over the first and second layers, wherein the self-assembled molecular layer has regions of etch selectivity; and etching the self-assembled molecular layer at the regions of etch selectivity until gate structures are formed over the first and second portions of the substrate.